An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Design

The FPGA technology mapping and synthesis problem for combinational circuits has been well studied. But for sequential circuits, most of the previous synthesis and mapping algorithms assume that the positions of ippops are xed and synthesize each combinational block independently. Retiming is a technique to reduce the clock period by repositioning ippops LeSa91]. With retiming, the previous mapping algorithms may not lead to an optimal solution of a sequential circuit by mapping each combinational block independently. Pan and Liu PaLi96b] recently proposed a novel algorithm, named SeqMapII, of technology mapping with retiming for the optimal clock period. The time complexity of their algorithm, however, is O(K 3 n 4 log(Kn 2) log n) for sequential circuits with n gates and targeting K-LUT based FPGAs, which is too high for medium and large size designs in practice (more than 20 hours of CPU time to get the optimal solution for a design of 134 gates on a SPARC10 workstation). In this paper, we present three strategies to improve the performance of the SeqMapII algorithm. First, we show that the monotone property of labels hold for sequential circuits and develop an eecient label update with single K-cut computation. Second, we propose a new K-cut computation method on partial ow networks, which are very small in practice. Finally, SCC (strongly connected component) partition is performed to eliminate many redundant label computation to further speedup the algorithm. In practice, our algorithm works in O(K 2 n 3 logn) time and O(Kn) space according to our experimental results. It is 210 4 times faster than SeqMapII-opt for computing optimal solutions and 2 times faster than SeqMapII-heu which uses very small expanded circuits as a heuristic.